The present invention relates generally to the production of semiconductor grade single crystal silicon used in the manufacture of electronic components, and more particularly to a heat shield assembly used in the growth of such semiconductor material.
Single crystal silicon, which is the starting material for most processes for the fabrication of semiconductor electronic components, is commonly prepared by the so-called Czochralski ("Cz") method. The growth of the crystal is most commonly carried out in a crystal pulling furnace. In this method, polycrystalline silicon ("polysilicon") is charged to a crucible and melted, a seed crystal is brought into contact with the molten silicon and a single crystal is grown by slow extraction. After formation of a neck is complete, the diameter of the crystal is enlarged by decreasing the pulling rate and/or the melt temperature until the desired or target diameter is reached. The cylindrical main body of the crystal which has an approximately constant diameter is then grown by controlling the pull rate and the melt temperature while compensating for the decreasing melt level. Near the end of the growth process but before the crucible is emptied of molten silicon, the crystal diameter must be reduced gradually to form an end-cone. Typically, the end-cone is formed by increasing the crystal pull rate and heat supplied to the crucible. When the diameter becomes small enough, the crystal is then separated from the melt.
Although the conventional Czochralski growth method has been satisfactory for growing single crystal silicon useful in a wide variety of applications, further improvements in the quality of the semiconductor material are desirable. As the width of the integrated circuit lines formed on the semiconductor material are reduced, the presence of defects in the crystal become of greater concern. A number of defects in single crystal silicon form in the crystal growth chamber as the crystal cools after solidification. Such defects arise, in part, because of the presence of an excess (i.e., a concentration above the solubility limit) of intrinsic point defects, which are known as vacancies and self-interstitials. Vacancies, as their name suggests, are caused by the absence or "vacancy" of a silicon atom in the crystal lattice. Self-interstitials are produced by the presence of an extra silicon atom in the lattice. Both kinds of defects adversely affect the quality of the semiconductor material.
Silicon crystals grown from a melt are typically grown with an excess of one or the other type of intrinsic point defect, either crystal lattice vacancies or silicon self-interstitials. It is understood that the type and initial concentration of these point defects in the silicon, which become fixed at the time of solidification, are controlled by the ratio v/G.sub.0, where v is the growth velocity and G.sub.0 is the instantaneous axial temperature gradient in the crystal at the time of solidification. As the value of v/G.sub.0 exceeds a critical value, the concentration of vacancies increases. Likewise, as the value of v/G.sub.0 falls below the critical value, the concentration of self-interstitials increases. Although neither form of defect is desirable, growth regimes which produce a predominance of vacancies are preferred, in general, by the semiconductor industry.
It is known to reduce the number density of intrinsic point defects by controlling v/G.sub.0 to grow a crystal lattice in which crystal lattice vacancies are the dominant intrinsic point defect, and by reducing the nucleation rate of agglomerated defects by altering (generally, by slowing down) the cooling rate of the silicon ingot from about 1100.degree. C. to 1050.degree. C. during the crystal pulling process. Another approach to dealing with the problem of agglomerated intrinsic point defects includes methods which focus on the dissolution or annihilation of agglomerated intrinsic point defects subsequent to their formation. Generally, this is achieved by using high temperature heat treatments of the silicon in wafer form. For example, Fusegawa et al. propose, in European Patent Application 503,816 A1, growing the silicon ingot at a growth rate in excess of 0.8 mm/minute, and heat treating the wafers which are sliced from the ingot at a temperature in the range of 1150.degree. C. to 1280.degree. C. to annihilate the defects which form during the crystal growth process. Such heat treatments have been shown to reduce the defect density in a thin region near the wafer surface. The specific treatment needed will vary depending upon the concentration and location of agglomerated intrinsic point defects in the wafer. Different wafers cut from a crystal which does not have a uniform axial concentration of such defects may require different post-growth processing conditions. Furthermore, such wafer heat treatments are relatively costly, have the potential for introducing metallic impurities into the silicon wafers, and are not universally effective for all types of crystal-related defects.
Still another approach to dealing with the problem of agglomerated intrinsic point defects is the epitaxial deposition of a thin crystalline layer of silicon on the surface of a single crystal silicon wafer.
This process provides a single crystal silicon wafer having a surface which is substantially free of agglomerated intrinsic point defects. Epitaxial deposition, however, substantially increases the cost of the wafer.
In order to facilitate predomination of vacancy defects, and avoid the presence of a radial vacancy/self-interstitial boundary ring in the crystal, v/G.sub.0 is controlled to be as high as possible. One way to increase the ratio is to increase the pull rate (growth velocity) of the crystal. However other factors such as diameter control of the crystal limit the amount the pull rate may be increased. The other way to attack the problem is to reduce the thermal gradient G.sub.0 in the crystal. In that regard, a heat shield may be disposed within the crucible which conserves heat at the liquid-gas-solid interface, by forming a partial thermal cavity, the heat lost from the free melt surface. In this way the instantaneous axial thermal gradient (G.sub.0) at the interface is reduced, which increases the ratio v/G.sub.0. However, shields of this type which are fixed in the crystal pulling furnace obstruct the crucible, making it difficult to load new semiconductor source material into the crucible prior to melting. Although a shield might be removed, it is not easy to replace the shield because the furnace must remain substantially sealed once the melting of the source material commences. Further, many conventional crystal pulling furnaces have so little space in the crystal growth chamber, that it is impractical to mount a fixed shield in the chamber.
The problem of space becomes even more critical when attempting to reduce the thermal gradient in the crystal in the range of 1100.degree. C. to 1050.degree. C. Physically, this temperature range occurs at a location in the single crystal silicon substantially above the level of the melt in the crucible. Thus, an even larger shield would be necessary in order to provide both for focusing heat at the liquid-gas-solid interface in the crucible and for retarding heat transfer above the crucible. Thus, there is presently a need for a compact, easily manipulated heat shield assembly which is capable of focusing heat at the liquid-gas-solid interface, and retarding heat transfer above the interface.